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Title: Formal Equivalence Checking and Design DeBugging
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Author: Huang, Shi-Yu
Co-Authors: Kwang-Ting Cheng
Description: Foreword
Preface
Ch. 1 Introduction 1
Ch. 2 Symbolic Verification 17
Ch. 3 Incremental Verification for Combinational Circuits 39
Ch. 4 Incremental Verification for Sequential Circuits 61
Ch. 5 AQUILA: A Local BDD-based Equivalence Verifier 91
Ch. 6 Algorithm for Verifying Retimed Circuits 111
Ch. 7 RTL-to-Gate Verification 123
Ch. 8 Introduction to Logic Debugging 139
Ch. 9 Error Tracer: Error Diagnosis by Fault Simulation 159
Ch. 10 Extension to Sequential Error Diagnosis 175
Ch. 11 Incremental Logic Rectification 189
Bibliography 211
Index 223
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