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Date: 02-14-05

Title: ASSET® integrates Lattice’s in-system configuration engine into its ScanWorks® JTAG system

ASSET® integrates Lattice’s in-system configuration engine into its ScanWorks® JTAG system


Concurrent programming of multiple logic devices can increase efficiency by 30 percent


Richardson, TX (Feb. 14, 2005) – ASSET InterTech Inc., (www.asset-intertech.com) an international leader in boundary-scan (JTAG/IEEE 1149.1) test and in-system programming (ISP), has integrated into its ScanWorks boundary scan environment Lattice Semiconductor’s ispVM System, a programming engine that supports the IEEE 1532 Standard for In-System Configuration.


The same ScanWorks system that applies boundary scan tests to an assembled circuit board can also program multiple on-board logic devices concurrently, reducing programming time and increasing the efficiency of manufacturing operations. Benchmark tests by ASSET have shown that programming times can be reduced by 30 percent or more.


Lattice Semiconductor, Hillsboro, OR, designs, develops and markets a broad range of programmable logic devices and software design tools. ASSET’s easy yet powerful ScanWorks boundary-scan test and ISP environment is currently used by leading electronics companies such as Cisco, Lucent Technologies, Alcatel, Agilent, BAE, Hewlett-Packard, Ericsson, Intel, Raytheon, Solectron, Rockwell Collins, SBS, EMC and others.


The new ScanWorks with 1532 concurrent programming capabilities has been trialed at Alcatel, a global supplier of communications equipment.


“From our experience with it, we can see that the concurrent programming capability of ScanWorks with IEEE 1532 has the potential to  save our organization considerable time,” said Doug Way, test engineer at Alcatel and a member of the IEEE working group that developed the IEEE 1532 specification. “The integration of IEEE 1532 capabilities into ScanWorks is very seamless. As a result, ScanWorks makes IEEE 1532 easy to use.”


Dave Bonnett, ASSET’s technical marketing manager, served as vice chairman of the IEEE 1532 working group.


“The IEEE 1532 working group tried to address the in-system configuration needs of the boundary-scan community as well as PLD tools vendors and the suppliers of in-circuit test (ICT) systems,” Bonnett said. “Being based on an industry standard allows the 1532 methodology to be deployed across a variety of test technologies. For example, designers can use 1532 on ScanWorks stations during development, manufacturing and test engineers can also tap into 1532 on ScanWorks manufacturing stations and, in addition,  technicians can utilize 1532  during high volume manufacturing on a ScanWorks for the Agilent 3070 ICT system.”


The IEEE 1532 standard uses the JTAG infrastructure on a circuit board to access on-board programmable logic devices (PLDs) and field programmable gate arrays (FPGAs) to load programming or configuration data into them. If multiple IEEE 1532 programmable devices are present, they all can be configured simultaneously, drastically reducing the time it would take to program each device one after the other. With Lattice’s ispVM System programming engine, ASSET’s ScanWorks is able to program any PLD or FPGA that conforms to the IEEE 1532 standard regardless of the supplier of the device.


“Our arrangement with Lattice demonstrates the strategic directions we have undertaken

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